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500 MHz to 1700 MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5357
FEATURES
RF frequency range of 500 MHz to 1700 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.6 dB SSB noise figure of 9.1 dB SSB noise figure with 5 dBm blocker of 19.5 dB Input IP3 of 26.6 dBm Input P1dB of 10.2 dBm Typical LO drive of 0 dBm Single-ended, 50 RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle 5 mm x 5 mm, 20-lead LFCSP 1500 V HBM/500 V FICDM ESD performance
FUNCTIONAL BLOCK DIAGRAM
IFGM
20
IFOP
19
IFON
18
PWDN
17
LEXT
16
ADL5357
VPIF 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3 BIAS GENERATOR COMM 4
13
VGS1
12
VGS0
APPLICATIONS
Cellular base station receivers Transmit observation receivers Radio link downconverters
COMM 5
6 7 8 9 10
11
LOI1
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
The ADL5357 uses a highly linear, doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL5357 incorporates an RF balun, allowing for optimal performance over a 500 MHz to 1700 MHz RF input frequency range using high-side LO injection for RF frequencies from 500 MHz to 1200 MHz and low-side injection for frequencies from 900 MHz to 1700 MHz. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than -46 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.6 dB and can be used with a wide range of output impedances.
The ADL5357 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5357 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<200 A) the circuit when desired. The ADL5357 is fabricated using a BiCMOS high performance IC process. The device is available in a 5 mm x 5 mm, 20-lead LFCSP and operates over a -40C to +85C temperature range. An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency (MHz) 500 to 1700 1200 to 2500 Single Mixer Single Mixer + IF Amp ADL5357 ADL5355 Dual Mixer + IF Amp
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08081-001
VLO3
LGM3
VLO2
LOSW
NC
ADL5357 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Performance ........................................................................... 4 3.3 V Performance ........................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 14 Spur Tables .................................................................................. 15 Circuit Description......................................................................... 16 RF Subsystem .............................................................................. 16 LO Subsystem ............................................................................. 17 Applications Information .............................................................. 18 Basic Connections ...................................................................... 18 IF Port .......................................................................................... 18 Bias Resistor Selection ............................................................... 18 Mixer VGS Control DAC .......................................................... 18 Evaluation Board ............................................................................ 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5357 SPECIFICATIONS
VPOS = 5 V, IS = 190 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 , unless otherwise noted. Table 2.
Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current Conditions Tunable to >20 dB over a limited bandwidth 500 Differential impedance, f = 200 MHz Externally generated 30 3.3 -6 240||0.4 5.0 0 12 50 450 5.5 +10 Min Typ 19 50 1700 Max Unit dB MHz ||pF MHz V dBm dB MHz V V V ns ns A A
730 1.0
1670
0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled 160 220 0.0 70
1 2
Apply the supply voltage from the external circuit through the choke inductors. The PWDN function is intended for use with VPOS 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5357
5 V PERFORMANCE
VPOS = 5 V, IS = 190 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious POWER SUPPLY Positive Supply Voltage Quiescent Current Total Quiescent Current Conditions Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 200 differential 5 dBm blocker present 10 MHz from wanted RF input, LO source filtered fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at -10 dBm fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz, each RF tone at -10 dBm Unfiltered IF output Min 7 Typ 8.6 14.9 9.1 19.5 26.6 62.8 10.2 -7 -46.7 -35 -69.2 -83.4 4.5 LO supply, resistor programmable IF supply, resistor programmable VPOS = 5 V 5 100 90 190 5.5 Max 9.5 Unit dB dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc V mA mA mA
22
-10 dBm input power -10 dBm input power
3.3 V PERFORMANCE
VPOS = 3.3 V, IS = 125 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 4.
Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) POWER INTERFACE Supply Voltage Quiescent Current Power-Down Current Conditions Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 200 differential fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at -10 dBm fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz, each RF tone at -10 dBm Min Typ 8.8 15.1 9.0 21.4 55.7 7.1 3.0 Resistor programmable Device disabled 3.3 125 150 3.6 Max Unit dB dB dB dBm dBm dBm V mA A
Rev. 0 | Page 4 of 24
ADL5357 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage, VPOS RF Input Level LO Input Level IFOP, IFON Bias Voltage VGS0, VGS1, LOSW, PWDN Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 1.2 W 25C/W 150C -40C to +85C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5357 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IFGM IFOP IFON PWDN LEXT
VPIF RFIN RFCT COMM COMM 1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
ADL5357
TOP VIEW (Not to Scale)
15 LOI2 14 VPSW 13 VGS1 12 VGS0 11 LOI1
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD. MUST BE SOLDERED TO GROUND.
VLO3 6 LGM3 7 VLO2 8 LOSW 9 NC 10
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4, 5 6, 8 7 9 10 11, 15 12, 13 14 16 17 18, 19 20 Mnemonic VPIF RFIN RFCT COMM VLO3, VLO2 LGM3 LOSW NC LOI1, LOI2 VGS0, VGS1 VPSW LEXT PWDN IFON, IFOP IFGM EPAD (EP) Description Positive Supply Voltage for IF Amplifier. RF Input. Must be ac-coupled. RF Balun Center Tap (AC Ground). Device Common (DC Ground). Positive Supply Voltages for LO Amplifier. LO Amplifier Bias Control. LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V. No Connect. LO Inputs. Must be ac-coupled. Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. Positive Supply Voltage for LO Switch. IF Return. This pin must be grounded. Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode. Differential IF Outputs (Open Collectors). Each requires an external dc bias. IF Amplifier Bias Control. Exposed pad. Must be soldered to ground.
Rev. 0 | Page 6 of 24
08081-002
ADL5357 TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VPOS = 5 V, IS = 190 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 1.1 k, R14 = 910 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
220 210
80 70 TA = -40C 60 TA = +25C
SUPPLY CURRENT (mA)
200
TA = -40C
INPUT IP2 (dBm)
50 40 30 20 10 0 700
TA = +85C
190 180 170 160 150 700
TA = +85C
TA = +25C
08081-034
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
12
14 13 12
Figure 6. Input IP2 vs. RF Frequency
10
TA = -40C
TA = +25C
CONVERSION GAIN (dB)
INPUT P1dB (dBm)
8
TA = +85C
11 10 9 8
TA = +25C TA = +85C
6
TA = -40C
4
2
7 6 700
750
800
850
900
950
1000 1050 1100 1150 1200
08081-015
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Power Conversion Gain vs. RF Frequency
35 30 25
TA = -40C TA = +25C
Figure 7. Input P1dB vs. RF Frequency
20 18 16
SSB NOISE FIGURE (dB)
INPUT IP3 (dBm)
TA = +85C
14 12 10 8 6 4 TA = +85C TA = +25C
20 15 10 5
TA = -40C
2 750 800 850 900 950 1000 1050 1100 1150 1200
08081-027
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
08081-021
0 700
0 700
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
Figure 8. SSB Noise Figure vs. RF Frequency
Rev. 0 | Page 7 of 24
08081-024
0 700
08081-019
ADL5357
250
VPOS = 5.25V
80 70 60
INPUT IP2 (dBm)
VPOS = 4.75V VPOS = 5V
VPOS = 5.0V
VPOS = 5.25V
200
SUPPLY CURRENT (mA)
VPOS = 4.75V
150
50 40 30 20
100
50
10
0 -40
-20
0
20
40
60
80
08081-035
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. Supply Current vs. Temperature
10 14 VPOS = 4.75V VPOS = 5.0V VPOS = 5.25V 13 12
Figure 12. Input IP2 vs. Temperature
9
CONVERSION GAIN (dB)
8
INPUT P1dB (dBm)
11 10 9 8 7 6 5
VPOS = 4.75V
VPOS = 5.0V
VPOS = 5.25V
7
6
5
-20
0
20
40
60
80
08081-046
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Power Conversion Gain vs. Temperature
35 33 31 29
INPUT IP3 (dBm)
11 12
Figure 13. Input P1dB vs. Temperature
VPOS = 5.0V VPOS = 5.25V VPOS = 4.75V
SSB NOISE FIGURE (dB)
VPOS = 5.0V
10
VPOS = 5.25V
27 25 23 21 19 17
-20 0 20 40
9
VPOS = 4.75V
8
7
60
80
08081-048
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Input IP3 vs. Temperature
Figure 14. SSB Noise Figure vs. Temperature
Rev. 0 | Page 8 of 24
08081-028
15 -40
6 -40
08081-049
4 -40
4 -40
08081-047
0 -40
ADL5357
220 210
SUPPLY CURRENT (mA)
80 70
TA = -40C TA = +25C
200
INPUT IP2 (dBm)
60
TA = -40C
50 40 30 20 10 0
TA = +85C
190 180
TA = +25C TA = +85C
170 160 150 30
08081-031
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 15. Supply Current vs. IF Frequency
12
12
Figure 18. Input IP2 vs. IF Frequency
10
CONVERSION GAIN (dB)
TA = -40C
TA = +25C
10
TA = +85C TA = -40C TA = +25C
TA = +85C
6
INPUT P1dB (dBm)
8
8
6
4
4
2
2
08081-013
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Power Conversion Gain vs. IF Frequency
35 30 25
TA = -40C TA = +25C
Figure 19. Input P1dB vs. IF Frequency
15 14 13
SSB NOISE FIGURE (dB)
TA = +85C
12 11 10 9 8 7
INPUT IP3 (dBm)
20 15 10 5 0 30
6
08081-020
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Input IP3 vs. IF Frequency
Figure 20. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 9 of 24
08081-011
5 30
08081-022
0 30
0 30
08081-017
ADL5357
12
12 TA = +85C
10
TA = -40C
TA = +25C
10
TA = -40C
CONVERSION GAIN (dB)
TA = +25C
TA = +85C 6
INPUT P1dB (dBm)
2 4 6 8 10
08081-014
8
8
6
4
4
2
2
-4
-2
0
2
4
6
8
10
LO POWER LEVEL (dBm)
LO POWER (dBm)
Figure 21. Power Conversion Gain vs. LO Power
30
TA = -40C
-10 0
Figure 24. Input P1dB vs. LO Power
25
TA = +85C
TA = +25C
-20
INPUT IP3 (dBm)
20
IF/2 SPURIOUS (dBc)
-30 -40 -50 -60 -70 TA = -40C TA = +85C 750 800 850 900 950 1000 1050 1100 1150 1200
08081-007 08081-008
15
10
TA = +25C
5
-80
6
4
2
0
2
4
6
8
10
LO POWER LEVEL (dBm)
08081-016
0
-90 700
RF FREQUENCY (MHz)
Figure 22. Input IP3 vs. LO Power
80 70 60 50 40 30 20
TA = -40C TA = +25C
Figure 25. IF/2 Spurious vs. RF Frequency
0 -10 -20
IF/3 SPURIOUS (dBc)
TA = +85C
-30 -40 -50 -60 -70 -80
TA = +25C TA = -40C 750 800 850 900 950
INPUT IP2 (dBm)
10 0 -6
-90
-4 -2 0 2 4 6 8 10
08081-018
-100 700
TA = +85C 1000 1050 1100 1150 1200
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 23. Input IP2 vs. LO Power
Figure 26. IF/3 Spurious vs. RF Frequency
Rev. 0 | Page 10 of 24
08081-023
0
-6
-4
-2
0
0 -6
ADL5357
100 MEAN: 8.59 SD: 0.14%
500
10
DISTRIBUTION PERCENTAGE (%)
80
400
8
60
300
6
40
200
4
20
100
2
08081-044
8.4
8.5
8.6
8.7
8.8
8.9
80
130
180
230
280
330
380
430
CONVERSION GAIN (dB)
IF FREQUENCY (MHz)
Figure 27. Power Conversion Gain Distribution
100
Figure 30. IF Port Return Loss
0 5
MEAN: 26.57 SD: 0.39%
DISTRIBUTION PERCENTAGE (%)
80
RF RETURN LOSS (dB)
10 15 20 25 30 35
60
40
20
INPUT IP3 (dBm)
08081-043
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 28. Input IP3 Distribution
100
0
Figure 31. RF Port Return Loss, Fixed IF
MEAN: 10.22 SD: 0.50%
DISTRIBUTION PERCENTAGE (%)
80
5
LO RETURN LOSS (dB)
10 SELECTED 15 UNSELECTED 20
60
40
20
25
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
INPUT P1dB (dBm)
Figure 29. Input P1dB Distribution
Figure 32. LO Return Loss, Selected and Unselected
Rev. 0 | Page 11 of 24
08081-038
9.6
9.9
10.2
10.5
10.8
08081-045
0
30 900
08081-029
0 24
25
26
27
28
29
40 700
08081-050
0 8.3
0 30
0
CAPACITANCE (pF)
RESISTANCE ()
ADL5357
70 0
65
-10 TA = +25C TA = +85C TA = -40C
LO SWITCH ISOLATION (dB)
60
LO-TO-RF LEAKAGE (dBm)
-20
55
-30 TA = +85C -40 TA = -40C
50
45
-50 TA = +25C 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
08081-026 08081-040
08081-039
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
08081-041
40 900
-60 900
Figure 33. LO Switch Isolation vs. LO Frequency
0 -5
Figure 36. LO-to-RF Leakage vs. LO Frequency
0 -5 -10
2LO LEAKAGE (dBm)
RF-TO-IF ISOLATION (dBc)
-10 -15 -20 -25 -30 -35 -40 -45 700 TA = +85C TA = -40C TA = +25C
-15 -20
2LO TO RF 2LO TO IF
-25 -30 -35 -40 -45 900
750
800
850
900
950
1000 1050 1100 1150 1200
08081-030
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 34. RF-to-IF Isolation vs. RF Frequency
0 TA = -40C -5
Figure 37. 2LO Leakage vs. LO Frequency
0
-10
TA = +85C
LO-TO-IF LEAKAGE (dBm)
3LO LEAKAGE (dBm)
TA = +25C
-10
-20
-15
-30
3LO TO RF 3LO TO IF
-20
-40
-25
-50
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
08081-025
-30 900
-60 900
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
Figure 35. LO-to-IF Leakage vs. LO Frequency
Figure 38. 3LO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
ADL5357
10 9 8
CONVERSION GAIN
15 14 13
NOISE FIGURE (dB)
08081-037
30
25
SSB NOISE FIGURE (dB)
CONVERSION GAIN (dB)
7 6 5 4 3 2 1 0 700
750
12
SSB NOISE FIGURE
20
11 10 9 8
VGS = 00 VGS = 01 VGS = 10 VGS = 11
15
10
7 6
5
800
850
900
950
-25
-20
-15
-10
-5
0
5
10
RF FREQUENCY (MHz)
BLOCKER POWER (dBm)
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency
20 18 16
30 28 26 24 22
Figure 42. SSB Noise Figure vs.10 MHz Offset Blocker Level
140 120 R9 LO SET RESISTOR
SUPPLY CURRENT (mA)
VGS = 00 VGS = 01 VGS = 10 VGS = 11 INPUT IP3
INPUT P1dB (dBm)
100 80 R14 IF SET RESISTOR 60 40 20 0 600
14 12 INPUT P1dB 10 8 6 700
20 18 16 1000 1050 1100 1150 1200
INPUT IP3 (dBm)
800
1000
1200
1400
1600
1800
RF FREQUENCY (MHz)
BIAS RESISTOR VALUE ()
Figure 40. Input P1dB and Input IP3 vs. RF Frequency
12 INPUT IP3 11 25 30
Figure 43. IF or LO Supply Current vs. IF or LO Bias Resistor Value
12 INPUT IP3 11 25 30
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
INPUT IP3 (dBm)
SSB NOISE FIGURE 9 CONVERSION GAIN 8 10 15
SSB NOISE FIGURE 9 CONVERSION GAIN 8 10 15
7
5
7
5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
LO BIAS RESISTOR VALUE (k)
IF BIAS RESISTOR VALUE (k)
Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias Resistor Value
Figure 44. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value
Rev. 0 | Page 13 of 24
08081-059
0.8
1.0
1.2
1.4
1.6
1.8
08081-012
6 0.6
0
6
0
INPUT IP3 (dBm)
10
20
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
10
20
08081-033
750
800
850
900
950
08081-036
08081-042
5 1000 1050 1100 1150 1200
0 -30
ADL5357
3.3 V PERFORMANCE
VPOS = 3.3 V, IS = 125 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted.
160 150 140
SUPPLY CURRENT (mA)
80 70 TA = +85C TA = +25C 60
TA = +25C
TA = -40C
INPUT IP2 (dBm)
130 120 110 100 90 80 70 60 700 750 800 850 900 950 1000 1050 1100 1150 1200 TA = +85C
50 40 30 20 10 0 700
TA = -40C
RF FREQUENCY (MHz)
08081-064
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 45. Supply Current vs. RF Frequency at 3.3 V
12
12
Figure 48. Input IP2 vs. RF Frequency at 3.3 V
10
TA = -40C
TA = +25C
10 TA = +25C
CONVERSION GAIN (dB)
8 TA = +85C 6
INPUT P1dB (dBm)
8
TA = +85C
6
TA = -40C
4
4
2
2
08081-060
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V
25 TA = -40C 20 TA = +25C 12 14
Figure 49. Input P1dB vs. RF Frequency at 3.3 V
SSB NOISE FIGURE (dB)
TA = +85C
INPUT IP3 (dBm)
10
TA = +85C
TA = +25C
15
8 TA = -40C 6
10
5
4
08081-062
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 47. Input IP3 vs. RF Frequency at 3.3 V
Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V
Rev. 0 | Page 14 of 24
08081-051
0 700
2 700
08081-063
0 700
0 700
08081-061
ADL5357
SPUR TABLES
All spur tables are (N x fRF) - (M x fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement system = -100 dBm.
5 V Performance
VPOS = 5 V, IS = 190 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 7.
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -41.3 -87.1 <-100 <-100 <-100 <-100 1 -4.8 0.0 -65.5 <-100 <-100 <-100 <-100 <-100 2 -15.8 -47.1 -73.4 <-100 <-100 <-100 <-100 <-100 <-100 <-100 3 -33.5 -37.9 -78.8 -94.0 <-100 <-100 <-100 <-100 <-100 <-100 <-100 4 -38.6 -57.9 -87.3 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -55.7 -57.3 -93.1 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -74.9 -92.1 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 M 7 8 9 10 11 12 13 14
N
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
3.3 V Performance
VPOS = 3.3 V, IS = 125 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V, and ZO = 50 , unless otherwise noted. Table 8.
M 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -50.8 -75.0 <-100 <-100 <-100 <-100 1 -9.9 0.0 -59.1 -93.8 <-100 <-100 <-100 <-100 2 -20.0 -50.1 -69.6 <-100 <-100 <-100 <-100 <-100 <-100 <-100 3 -43.5 -37.1 -71.4 -82.0 <-100 <-100 <-100 <-100 <-100 <-100 <-100 4 -40.8 -53.5 -81.6 -99.8 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -62.2 -56.0 -90.7 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -72.8 -86.7 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 7 8 9 10 11 12 13 14
N
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
Rev. 0 | Page 15 of 24
ADL5357 CIRCUIT DESCRIPTION
The ADL5357 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of an integrated, low loss RF balun, passive MOSFET mixer, sum termination network, and IF amplifier. The LO subsystem consists of an SPDT-terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 51.
IFGM
20
RF SUBSYSTEM
The single-ended, 50 RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 500 MHz to 1700 MHz. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M x N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and also in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that are required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 . If operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure 41, Figure 43, and Figure 44 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.)
IFOP
19
IFON
18
PWDN
17
LEXT
16
ADL5357
VPIF 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3 BIAS GENERATOR COMM 4
13
VGS1
12
VGS0
COMM 5
6 7 8 9 10
11
LOI1
NC = NO CONNECT
Figure 51. Simplified Schematic
Rev. 0 | Page 16 of 24
08081-001
VLO3
LGM3
VLO2
LOSW
NC
ADL5357
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1100 MHz. The best operation is achieved with either high-side LO injection for RF signals in the 500 MHz to 1200 MHz range or high-side injection for RF signals in the 900 MHz to 1700 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 500 MHz to 1700 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5357 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from -6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5357 has a power-down mode that permits the dc current to drop to <200 A. All of the logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn. All pins, including the RF pins, are ESD protected and have been tested up to a level of 1500 V HBM and 500 V CDM.
Rev. 0 | Page 17 of 24
ADL5357 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5357 mixer is designed to downconvert radio frequencies (RF) primarily between 500 MHz and 1700 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 52 depicts the basic connections of the mixer. It is recommended to ac couple RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN capacitor value of 8 pF is recommended to provide the optimized RF input return loss for the desired frequency band.
BIAS RESISTOR SELECTION
Two external resistors, RBIAS IF and RBIAS LO, are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure 41, Figure 43, and Figure 44 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and IP3 performance.
MIXER VGS CONTROL DAC
The ADL5357 features two logic control pins, VGS0 (Pin 12) and VGS1 (Pin 13), that allow programmability for internal gate-tosource voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults both VGS0 and VGS1 to ground. Power conversion gain, IIP3, NF, and IP1dB can be optimized, as is shown in Figure 39 and Figure 40.
IF PORT
The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately 200 , as seen in Figure 30, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Table 3. When a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 52.
Rev. 0 | Page 18 of 24
ADL5357
+5V
100pF 150pF 470nH 470nH 4:1 IF OUT
RBIAS IF +5V 4.7F +5V 10pF
1 20 19 18 17
10k
16
ADL5357
15
22pF LO2 IN
8pF RF IN
2 14
+5V 10pF
3
13
10pF
0.1F
BIAS GENERATOR
4 12
22pF
5 6 7 8 9 10 11
LO1 IN
RBIAS LO +5V 10pF 10pF
10k
08081-005
Figure 52. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5357 EVALUATION BOARD
An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 53. The evaluation board is fabricated using Rogers(R) RO3003 material. Table 9 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 54 to Figure 57.
L5 470nH VPOS C18 100pF C19 100pF L4 470nH R25 0 R14 910 R24 0 L3 0 R21 10k C17 150pF R1 0
T1
IF1-OUT
PWR_UP
IFGM
IFON
IFOP
PWDN
LEXT
C12 22pF LO2_IN LOI2 VPSW VPOS
VPOS RF-IN C1 8pF
C2 10F
C21 10pF
VPIF RFIN RFCT COMM COMM
LGM3 VLO3 VLO2 LOSW NC
C20 10pF C22 1nF VGS1 VGS0
R22 10k R23 15k
C5 0.01F
C4 10pF
ADL5357
VGS1 VGS0 LOI1
LO1_IN C10 22nF
VPOS
C6 10pF
R9 1.1k C8 10pF
LOSEL VPOS R4 10k
08081-006
Figure 53. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
ADL5357
Table 9. Evaluation Board Configuration
Components C2, C6, C8, C18, C19, C20, C21 C1, C4, C5 T1, C17, L4, L5, R1, R24, R25 Description Power Supply Decoupling. Nominal supply decoupling consists of a 10 F capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. RF Input Interface. The input channels are ac-coupled through C1. C4 and C5 provide bypassing for the center taps of the RF input baluns. IF Output Interface. The open-collector IF output interfaces are biased through pull-up choke inductors L4 and L5. T1 is a 4:1 impedance transformer used to provide a single-ended IF output interface, with C17 providing center-tap bypassing. Remove R1 for balanced output operation. LO Interface. C10 and C12 provide ac coupling for the LO1_IN and LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN is enabled when LOSEL is pulled to logic high. PWDN Interface. R21 pulls the PWDN logic low and enables the device. The PWR_UP test point allows the PWDN interface to be exercised using the external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. Bias Control. R22 and R23 form a voltage divider to provide 3 V for logic control, bypassed to ground through C22. VGS0 and VGS1 jumpers provide programmability at the VGS0 and VGS1 pins. It is recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. R14 sets the bias point for the internal IF amplifier. Default Conditions C2 = 10 F (size 0603), C6, C8, C20, C21 = 10 pF (size 0402), C18, C19 = 100 pF (size 0402) C1 = 8 pF (size 0402), C4 = 10 pF (size 0402), C5 = 0.01 F (size 0402) T1 = TC4-1W+ (Mini-Circuits), C17 = 150 pF (size 0402), L4, L5 = 470 nH (size 1008), R1, R24, R25 = 0 (size 0402) C10, C12 = 22 pF (size 0402), R4 = 10 k (size 0402)
C10, C12, R4
R21
R21 = 10 k (size 0402)
C22, L3, R9, R14, R22, R23, VGS0, VGS1
C22 = 1 nF (size 0402), L3 = 0 (size 0603), R9 = 1.1 k (size 0402), R14 = 910 (size 0402), R22 = 10 k (size 0402), R23 = 15 k (size 0402), VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 21 of 24
ADL5357
Figure 54. Evaluation Board Top Layer
08081-055
Figure 56. Evaluation Board Power Plane, Internal Layer 2
08081-056
Figure 55. Evaluation Board Ground Plane, Internal Layer 1
Figure 57. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
08081-058
08081-057
ADL5357 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
15 16 20 1
PIN 1 INDICATOR
PIN 1 INDICATOR
4.75 BSC SQ
0.65 BSC
EXPOSED PAD
(BOTTOM VIEW)
5
3.20 3.10 SQ 3.00
TOP VIEW 0.70 0.65 0.60
0.75 0.60 0.50
11
10
6
2.60 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.90 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 58. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-20-5) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5357ACPZ-R7 1 ADL5357ACPZ-WP1 ADL5357-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-20-5 CP-20-5
042209-B
0.35 0.28 0.23
0.05 MAX 0.01 NOM COPLANARITY 0.05 0.20 REF
Ordering Quantity 1,500, 7" Tape and Reel 36, Waffle Pack 1
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADL5357 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08081-0-7/09(0)
Rev. 0 | Page 24 of 24

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